GitHub - pranav-avn/Verilog

Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
.gitignore		.gitignore
4bitCountersim.png		4bitCountersim.png
CLA_modular.v		CLA_modular.v
flipflop.png		flipflop.png
fourBitCounter.v		fourBitCounter.v
fourbitadder.v		fourbitadder.v
msFF.v		msFF.v
mult.v		mult.v
srLatch.v		srLatch.v
srLatchsim.png		srLatchsim.png