Talk:Instructions per second

Reference for the Timeline Table

I found a possible reference for the still unreferenced entries in the timeline table. It is from a book from Kai Qian,David den Haring,Li Cao named Embedded Software Development with C. It can be found under google books: http://books.google.com/books?id=aB1EgF0jB-MC&pg=PA8&lpg=PA8&dq=AMD+Athlon+%223,561+MIPS%22+-wiki&source=bl&ots=pG_B87T73t&sig=P4YYT12GS7tH9quVl9jiGUo5084&hl=de&ei=MQQbTYLmIYvwsgb91OH5DA&sa=X&oi=book_result&ct=result&resnum=1&ved=0CBUQ6AEwAA#v=onepage&q=AMD%20Athlon%20%223%2C561%20MIPS%22%20-wiki&f=false

Critics on MIPS

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The article has a lengthy description of the acronyms critics of MIPs use, but does not state why they are critical of the metric. I suggest explaining why they are, for those people who read the article and have not taken computer architecture.

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—Preceding unsigned comment added by 65.6.47.129 (talk) 19:25, 2 September 2007 (UTC)

Those critics are personal opinions that are not appropriate for Wikipedia. I think the critics are mainly caused by ignorance of what MIPS means. Quite many people seem to mix MIPS with MNOPS (Million NOP instructions per second). That is, they assume that you can take the fastest possible execution time of the fastest instruction (such as NOP), calculate how many such instructions could be executed in second, and then call that MIPS. That would, of course, not be an useful method for comparing processor speeds. But that is not MIPS. MIPS is the average execution time of insturctions in real world applications.

-- PauliKL (talk) 13:34, 14 March 2008 (UTC)

Unfortunately this is not true. MIPS is highly dependent on the application that is used to calculate it. If a clever compiler reduces the use of time-eating instructions, this can possibly result in a lower MIPS value, although the processor is as fast as before. A simple example would be this: consider our processor contains only two instructions, add and multiply. In a sample program, compiled with a dumb compiler, all multiplications are displaced by multiple additions. Another compiler might use the builtin multiplication. Therefore, as one addition is faster than one multiplication, the first application results in a lower CPI (cycles per instructions) value, and the second one in a higher CPI. As a result (MIPS depends on CPI), the second application results in a lower MIPS value, although we are using the same processor. ( http://devel-rok.informatik.hu-berlin.de/svn/TI2/2006/folien/pdf/eng_ca03.pdf ) Is there more to add?

--141.20.192.251 (talk) 16:59, 15 July 2008 (UTC)

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The acronym MIPS is inherently wrong due to the fact the unit of measure of time "second" has to be specified accordingly to the international standards spec. as a lowercase "s".

Following the correct example in the first sentence by the user "65.6.47.129" above, MIPs is the formally correct horthografy.

-- AT 213.156.52.121 (talk) 19:20, 27 April 2008 (UTC)

No. The correct acronym is MIPS, since that is the acronym that has been commonly aggreed. If international standard specs (SI) was to be used, the acronym would be MI/s. But that is not the point. The main thing is what MIPS actually means and what does it measure. --PauliKL (talk) 18:54, 15 May 2008 (UTC)

Changes

Removed Pentium 4 data for error. Pentium 4s typically have MIPS between 3,000 and 20,000, depending on year of release.

Also removed data based on erroneous formula.

Added Year 2004 data for budget 32 bit and 64 bit PCs.

Several instructions per clock cycle

• Is that right about 20,000 MIPS for the Pentium and 10,000 for the Celeron? Can they really do several instructions per clock tick? Bubba73 19:15, 12 Jun 2005 (UTC)

• Theoretically yes. Starting from the 486 which is a 386CPU and 387FPU on the same die, most processors can theoretically do more than 1 instruction per cycle. Note that cycle does not equal clock.

That is not true. 486 can definitely not execute more than 1 instruction per clock cycle. And many instructions take more than 1 clock cycle, so the average is significantly less than 1 instruction/cycle. Adding FPU on same die does not change that. It is insignificant whether the FPU is on the same die or on different die. It does not change the way the processor works, and it does not have effect on the MIPS value. Since the days of the first FPU's, everybody has known the fact that adding FPU does not change MIPS value. MIPS is about integer performance of the CPU itself. It does not take account floating point calculations. And adding external units such as graphics processors does not have effect on MIPS value either. - PauliKL (talk) 21:27, 24 February 2008 (UTC)

P.S. Added the missing headings on talk page - PauliKL (talk) 22:22, 24 February 2008 (UTC)

• Ever since the first Pentium processor they have been superscalar, which means they can perform more than one instruction per clock. Now for some modern MIPS calculations: the K7 and K8 (Athlon and Althon 64 from AMD) have 3 integer units each and can issue 3 insructions per clock, and can complete most non-memory integer operations in a single clock. The fastest single-core Athlon 64 is 2.8GHz, which gives a theoretical limit of 2.8e9 * 3 / 1e6 = 8400 MIPS. The Intel Pentium 4 has 2 simple integer units and one complex unit. It can perform a select subset of simple integer operations (add,subtract, and shifts on the Prescott) at a rate of 4 instructions per clock, or a single less simple operation. The fastest single-core Pentium 4 is 3.8GHz, which gives a peak of 15200 MIPS if you are doing the 4 instructions per clock, or down to 3800 MIPS for less-simple instructions. None of this includes things you can do with the SIMD instructions. Given the ambiguity in the Pentium calculations I'll just start by adding the Athlon 64 to give an idea of current speed of modern processors.

• According to SySoft SANDRA Dhrystone ALU benchmark, an Athlon FX-57 clocked at 2.8GHz yield 12000 MIPS, an Athlon 64 X2 3800+ with two cores at 2GHz yield 17200 MIPS, using the same benchmark, I reached 25150 MIPS by overclocking my Athlon 64 X2 3800+ to 2.8GHz. I took the liberty to edit the Athlon 64 MIPS accordingly, if you don't beleive me, 'bench 'em yourself.

• MIPS is now largely replaced by MTOPS which manufacturers are required to disclose by law. (United States Department of Commerce Export Administration Regulations 15 CFR 774 (Advisory Note 4 for Category 4). )

• Links to MTOP calculations : [[1]]

[[2]]

Note that the above post is several years old and CTP is no longer required by the US government for export purposes. The Adjusted Peak Performance replaced CTP back in April 2006 but was itself replaced less than two years later. As seen in this Intel press release in November 5, 2007 the US government published amendments to the Export Administration Regulations 15 CFR which requires exporters to use the metric of Gigaflops (GFLOPS) to measure processor performance. --GrandDrake (talk) 05:57, 19 June 2010 (UTC)

Timeline

• Aren't timelines usually in chronological order? Shogun 01:07, 21 March 2006 (UTC)

yep, they are. I corrected the table. jidan 15:56, 15 May 2006 (UTC)

New proposed timeline

Hi, instead modifying the table inside the article, I write here the new proposed timeline based on http://www.frc.ri.cmu.edu/users/hpm/book97/ch3/processor.list.txt. However the last entries with the processor name only (from Intel pentium pro) should be removed/changed, because I think that is more realistic to calculate the IPS for the enteire system (CPU/bus/memory) and not only the processor. I also found very useful the cost of the system compared to the value of USD in the 1997, to understand the customer target. The sources are various (specint, speedmark, winsscore..) compared to the MIPS. May be not perfect, but I think it is a good point to start. Please to leave some comment. --Trek00 02:54, 5 February 2007 (UTC)

Processor	IPS	Year	Cost (USD 1997)
Pencil and Paper	0.0119 IPS	1892
ENIAC	2.89 kIPS	1946	600'000
UNIVAC I	5.75 kIPS	1951	930'000
Whirlwind	69.4 kIPS	1955	200'000
Atlas	1.4 MIPS	1961	5'000'000
CDC 6600	8.76 MIPS	1964	5'000'000
CDC 7600	25.7 MIPS	1969	10'000'000
IBM System/370-195	17.3 MIPS	1972	8'000'000
Altair 8800 (Intel 8080 at 2 MHz)	10 kIPS	1974	500
Cray 1	150 MIPS	1976	10'000'000
VAX 11/780	1 MIPS	1977	200'000
Apple II	20 kIPS	1977	1'300
Commodore 64	200 kIPS	1982	500
Macintosh 128K (Motorola 68000 at 8 MHz)	520 kIPS	1984	2'500
Cray 2	824 MIPS	1985	10'000'000
Macintosh II (Motorola 68020)	2.5 MIPS	1987	3'000
PC Brand 386/25 (Intel 386DX at 25 MHz)	4.3 MIPS	1988	2'450
Amiga 3000 (Motorola 68030)	12.5 MIPS	1990	3'300
Gateway 486DX2/66 (Intel 486DX at 66 MHz)	30.9 MIPS	1991	3'900
Power Macintosh 7100/66 (PowerPC 601 at 66 MHz)	100 MIPS	1994	2'899
ARM 7500FE	35.9 MIPS at 40 MHz	1996
Gateway G6-200 (Intel Pentium Pro at 200 MHz)	350 MIPS	1997	2'949
Power Macintosh G3 (PowerPC G3 at 266 MHz)	500 MIPS	1997	2'000
Zilog eZ80	80 MIPS at 50 MHz	1999
Intel Pentium III at 500 MHz	820 MIPS	1999	2'500
Power Macintosh G4 (PowerPC G4 at 450 MHz)	856 MIPS	1999	2'500
ASCI White	10000000 MIPS	2000	110'000'000
AMD Athlon	3561 MIPS at 1.2 GHz	2000
AMD Athlon XP 2400+	5935 MIPS at 2.0 GHz	2002
Pentium 4 Extreme Edition	9726 MIPS at 3.2 GHz	2003
System X	20000000 MIPS	2004	6'000'000
ARM Cortex A8	2000 MIPS at 1.0 GHz	2005
Xbox360 IBM "Xenon" Triple Core	6400 MIPS at 3.2 GHz	2005
IBM Cell All SPEs	12096 MIPS at 3.2 GHz	2006
AMD Athlon FX-57	12000 MIPS at 2.8 GHz	2005
AMD Athlon 64 3800+ X2 (Dual Core)	14564 MIPS at 2.0 GHz	2005
AMD Athlon FX-60 (Dual Core)	18938 MIPS at 2.6 GHz	2006
Intel Core 2 X6800	27079 MIPS at 2.93 GHz	2006
IBM Cell BE (All the SPEs)	25600 MIPS (FLOPS) at 3.2 GHz	2006
Intel Core 2 Extreme QX6700	57063 MIPS at 3.33 GHz	2006

Cell Data is blatantly incorrect

Guys -- The data you posted about the Cell processor is just plain incorrect. Please update the page. For the record:

Cell runs at 3.2 GHz. Cell has one dual-threaded fully 64-bit Power Architecture core. This core, not including its AltiVec vector processor, does 6400 MIPS... although these are 64-bit instructions so the comparison to 32-bit processors is really not too valid. (Should we claim that it's 12800 "32-bit MIP equivalents"?) In ADDITION to the above, the Cell has 8 single-threaded 128-bit processor cores. That adds 25600 MIPS or 102400 32-bit MIP equivalents... for a total of 38400 (115200).

FLOPS have nothing to do with the above. In FLOPS, the Cell does over 200 single-precision GFLOPS and in the high teens in double precision. As of today (30 Mar 2007), information on the next-generation processor has been released... although I am not at liberty to disclose its performance until someone cites it.

The figure you cited was not a peak value (as cited for other processors). Instead, you took the performance on a given benchmark (Linpack) in FLOPS... which are not comparable to MIPS.

The Cell Team at IBM

No, you can not multiply the MIPS value by 2 using the excuse that processor has some 64 bit instructions. One 64 bit instruction is still just one instruction. And, let's face it, 64 bit instructions are rarely used in real world applications. After all, 64 bit data is quite rare. Most common data is 8 bit (character data, 8 bit/channel RGB data etc.). In addition, most applications use only 32 bit instruction set in order to be compatible with older processors, so 64 bit processor is no faster than 32 bit one. But even if the program is compiled to use 64 bit insturctions, it will only be around 2% to 5% faster than the 32 bit version.

Indeed, FLOPS measurement should not be mixed with MIPS. MIPS is only about integer performance. No matter how powerful FPU is included with the CPU, it does not have effect on the MIPS value of the CPU.

There is no such thing as "peak value" in MIPS measurement. MIPS is the average number of instructions executed by the processor when running a real world application. (Well, the term "peak MIPS" is sometimes used to say that it is the speed of the CPU when the application fully fits in L1 cache so that the memory access is not slowing down the operation. Which is the case with Dhrystone benchmark, for example.)

-- PauliKL (talk) 22:09, 24 February 2008 (UTC)

Given MIPS ratings not correct

The MIPS ratings given in the table seem to be incorrect. For example, 8080 at 2 MHz has been given value 640 kIPS (0.64 MIPS), which is impossible. The fastest instructions on 8080 take 4 clock cycles. Thus, 2 MHz 8080 can execute maximum of 0.5 million instructions per second.

However, max number of instructions per second is not MIPS. MIPS is calculated from weighted average of instruction execution times.

I recall Intel has given 8080 rating of 0.08 MIPS, which sounds more correct, considering the fact that a 8 bit processor needs multiple instructions to perform a single 32 bit operation.

Another example: Zilog eZ80 has been given rating of 80 MIPS at 50 MHz. As far as I know, eZ80 is not a superscalar processor, so it can not execute more than 1 instruction / clock cycle. Since it is a 8 bit processor, the MIPS rating must be significantly less than 50 MIPS.

PauliKL (talk) 18:08, 23 January 2008 (UTC)

And youl English wliting not colect, eithel. Soly about that. --AVM (talk) 22:17, 14 February 2009 (UTC)

PauliKL does not seem to understand what MIPS means. That may be partly because it is not a well defined term in general, but here I thought it was defined in terms of the speed of executing native instructions. That means no compensation is made for what the instructions are doing.

I remember (although it has been a long time) that the 8080 can execute instructions as fast a 3 clock cycles. The basic instruction operation has three steps labeled T1, T2 and T3 which derive from the original 8008 which used three clock cycles to access memory over a single 8 bit port; output upper address, output lower address, input or output data. The 8080 retained the three clocks per machine cycle concept even though it could output the entire address and data in parallel.

http://www.allaboutcircuits.com/vol_4/chpt_16/5.html

Gnuarm (talk) 16:57, 3 February 2010 (UTC)

The whole table seems to be fed with wrong data. For example, the cited 23.8 IPS for a Core i7 Extreme 965 cannot be correct. Any Nehalem-based CPU is a 4-way superscalar CPU, i.e. it can execute at most four instructions per clock cycle (peak throughput). Having four cores (i7 Extreme 965) yields a theoretical maximum of 4*4 = 16 instructions per clock cycle. Thus, the 23.8 IPS number is clearly too high. --85.216.120.3 (talk) —Preceding undated comment added 16:49, 1 December 2010 (UTC).

edit: I think the whole confusion is caused by the numbers from Sisoft Sandra (or the inability to think and interpret those numbers by whoever used it as a source for its high IPS claim): Sisoft Sandra probably uses SIMD instructions to maximize throughput (SSE2/3 etc.) but counts every sub-instruction in a large SIMD-word as one executed instruction. For instance, if computing several 32 bit numbers, it uses the 128 bit SSE1/2/3 format to do four 32bit calculations in parallel. Although the throughput is equivalent to four single 32 bit operations, this is actually _one_ instruction executed, not four! If for example the processor is executing two of those SIMD instructions in parallel, those yield only an IPS of two. The instruction pipeline of the processor is incapable of processing eight (i.e. two times four) instructions per clock cycle. The hardware is simple not capable of doing that! So, in this example (Core i7 Extreme 965), it is simply wrong claiming a higher value of four IPS per core (or sixteen IPS in total). --85.216.120.3 (talk) 17:04, 1 December 2010 (UTC)

Sisoft Sandra does not count instructions. (In fact, I don't think it is even possible to count instructions without using dedicated debug hardware.) It uses Dhrystone test and then displays the results as MIPS. So, the unit used is actually Dhrystone-MIPS. However, the test used is not exactly the original Dhrystone test, but a multi-threaded, 32/64-bit variant, so the results are not 100% comparable with the original. (See the FAQ).

Maybe there should be separate columns for "IPS" (which usually means execution speed of NOP instructions) and Dhrystone-MIPS. --PauliKL (talk) 11:29, 5 December 2010 (UTC)

Seems the Freescale page for the 68060 gives different values. But maybe it's due to newer fabrication process ? Mmu man (talk) 19:20, 18 December 2010 (UTC)

MIPS = MHz?

If a microprocessor can execute a singular instruction million times per second (MHz), then why can't it execute a million unique instructions within the same timeframe (MIPS)? What is the game-changing constraint here? This article does not explain this rather bizarre behaviour.Anwar (talk) 10:44, 15 May 2008 (UTC)

Huh? What do you mean? MHz is unit of frequency, not unit of instructions per second. In context of processors, MHz is usually used to measure the clock frequency. Traditional CISC processor may require multiple clock cycles to execute one instruction, so they deliver less than 1 MIPS/MHz. RISC processors typically execute every instruction in one clock cycle. In that case, they would execute about as many instructions per second as the MHz value would indicate. Number of instructions executed per second is not same as MIPS, but with 32-bit processors, it is quite close. However, there are processors that can execute multiple instructions in parallel (superscalar). Further, there are processors with multiple cores. These deliver more than 1 MIPS/MHz. --PauliKL (talk) 19:10, 15 May 2008 (UTC)

IBM 704 & IBM 7030

Could someone add the Mips of the IBM 704 (1954) and the IBM 7030 (1961) to this table? I'm too dumb to do so. tnx in advance. See also new proposed timeline above. Aleichem (talk) 20:37, 8 June 2008 (UTC)

IPS/Hz

There's something wrong with the IPS/Hz metric. In SI base units a hertz is "1/second". Thus,

${\frac {IPS}{Hz}}={\frac {instructions/second}{1/second}}={\frac {instructions}{second}}\times {\frac {second}{1}}=instructions$

Just plain instructions. It does not make sense to me. Also, since IPS and CPU clock frequency are both unreliable performance metrics^{([3], page 13)}, their ratio is pretty much worthless anyway. —ZeroOne (talk / @) 11:40, 3 April 2010 (UTC)

It seems to be the number of instructions per clock cycle.--Patrick (talk) 15:29, 3 April 2010 (UTC)

That's kind of what I figured too. It just does not make sense to me that a desktop computer could execute thousands of instructions per clock cycle, as has been marked to be the case for several systems in the article. A clock cycle is what makes the CPU 'tick', nothing can happen faster than in one clock cycle. A quad-core processor could, of course, execute four instructions per second, etc. It seems to me that in this article MIPS refers to something else than the obvious. Weicker[4] lists five possible interpretations of the concept of MIPS that manufacturers give for their products. One of the interpretations, a common one according to the author, is "VAX MIPS". This is a factor relative to the VAX-11/780. This could be the one that is being used here. Anyway, I'm in favor of dumping the entire table because collecting statistics of a meaningless indicator of processor speed is, well, meaningless. At least the newer than 1970s computers could be dropped, because that's about when the original concept of MIPS started to fall apart anyway. —ZeroOne (talk / @) 23:39, 3 April 2010 (UTC)

The largest value in the table is 45, not thousands.--Patrick (talk) 06:11, 4 April 2010 (UTC)

Oops, my bad. The numbers were presented in different precision and I got confused. I have now rounded them all to just one decimal place. Anyway, I think the article needs to explain why is it possible to have, say, 45 instructions per clock cycle. I suppose it's got to do with superscalarity, branch prediction, etc, but in any case the 45 must be a peak number that is impossible for the system to sustain. Right? —ZeroOne (talk / @) 10:43, 5 April 2010 (UTC)

Rounding all values to 1 decimal was not a good idea. It would be OK to round 1234.56 to 1234.6, but when you round 0.25 to 0.3, you are creating a big error. For example, Intel 8080 now has value of 0.3 instructions/clock cycle, which means that average instruction execution time would be 3.33 cycles. However, on 8080 even the fastest instruction takes 4 clock cycles, and some instructions up to 18 cycles. --PauliKL (talk) 15:12, 8 April 2010 (UTC)

MIPS is actually a good measure for CPU performance, definitely not "worthless". The expression "meaningless indicator of processor speed" is used by ignorant people who do not know what MIPS means. Of course you should realize that MIPS only measures CPU performance. There are many other factors that affect the computer performance, such as the speed of memory bus, display controller and hard disk.

On the other hand, MIPS by itself does not measure the performance, it is just an unit used to display the performance value whichever method is used to measure it. There are good and not so good methods to do the measurement, just like there are many methods to measure temperature. Originally, the measurement was done by calculating a weighted average of specific instruction set (e.g. VAX instruction set for VAX MIPS). That was a good method, but laborious, so later many of the MIPS values were measured by running some benchmark and then comparing the results to known computers (e.g. Dhrystone MIPS).

But, as I have said before, the values in the table are wrong. For example, the correct value (according to Intel) for 8080 is 0.04 MIPS, not 0.5 MIPS. For newer processors, the values seem to be just pulled out of a hat. --PauliKL (talk) 16:03, 8 April 2010 (UTC)

One of the problems with MIPS as the unit of CPU performance is that different CPU architectures get different amounts of work done per instruction. Thus a 10 MIPS CPU can well be faster than a 20 MIPS CPU. —ZeroOne (talk / @) 12:24, 10 April 2010 (UTC)

No. The problem with MIPS is that ignorant people do not understand what MIPS means, and therefore they have all kind of false beliefs. In reality, 10 MIPS CPU can never be faster than 20 MIPS CPU (in integer calculations), since, by definition, 20 MIPS is twice as much power as 10 MIPS.

Back in the 70'ies and 80'ies, when actual calculated MIPS values were still used, the standard unit was VAX MIPS. It is based on VAX 11/780 instruction set (not the target machine's instruction set). The amount of work done depends on what VAX can do with the instructions, now what the target machine instructions do. If the target machine requires multiple instructions to perform one VAX instruction, the calculated instruction execution time is the sum of those instructions. That is why 8-bit processors have such a low MIPS ratings. For example, 8085 processor running at 4 MHz can execute up to 1 million instructions per second, but it's processing power (according to Intel) is only 0.08 MIPS.

Later, MIPS values where usually derived from benchmarks. If CPU A (rated at 10 MIPS) executes a benchmark in 20 seconds, and CPU B executes the same benchmark in 10 seconds, CPU B will have rating of 20 MIPS. How could CPU A still be more powerful than CPU B? --PauliKL (talk) 19:49, 11 April 2010 (UTC)

By definition MIPS = n / (t * 10^6) where n is the number of instructions executed and t is the time it took to execute those instructions, in seconds. It does not follow that a 20 MIPS CPU is always faster than a 10 MIPS CPU. An instruction of a CISC CPU could equal, say, 4 instructions of a RISC CPU. If the CISC CPU then performs at 10 MIPS, it would be equal to a 40 MIPS RISC CPU. Clearly the 10 MIPS CISC CPU would then be faster than a 20 MIPS RISC CPU. —ZeroOne (talk / @) 22:02, 11 April 2010 (UTC)

No. That is not the definition of MIPS. And what do you mean by "instructions executed"? What instructions? Executed when? As I already explained, the actual MIPS rating is the weighted average of the execution times of all instructions in some specific instruction set (e.g. VAX instruction set). The weighting factor depends on how common the instruction is in real world applications. If a RISC processor requires multiple instructions to perform one VAX instruction, the sum of the execution times of those instructions is counted as one instruction in MIPS calculations. Dhrystone MIPS, on the other hand, is the result of Drystone test normalized into MIPS scale. It does not count the instructions at all.

One CISC processor instruction definitely does not equal 4 RISC instructions. The studies show that a RISC processor typically needs 10% more instructions to execute a task than CISC processor. So, if executing an application requires 10 million instructions in CISC, it would require approximately 11 million instructions in RISC. If CISC processor needs 1 second to execute the task and RISC processor needs 0.5 seconds, then clearly RISC processor is more powerful. --PauliKL (talk) 16:46, 12 April 2010 (UTC)

By "instructions" I mean the individual instructions the processor executes: loads, stores, register manipulations, etc. They are executed when the application is being executed, obviously, because applications are made out of those instructions. The definition of MIPS I gave you is from Measuring Computer Performance : A Practitioner's Guide by David Lilja, ISBN 9780521641050. What makes you think Lilja, a published author, is "ignorant"? Can you give me an equally credible source for your interpretation of the MIPS figure?

I did not ask what you mean by "instructions". The question is, which instructions? Which application? What is that legendary "The Application" that is used to define which instructions are counted? The reason why ignorant people think MIPS is bad is because they assume they can just use any application they like, even one that contains nothing but NOP instructions. In reality, the weight factors used in VAX MIPS calculations were based on statistics from huge amount of real world applications run in VAX. The reliable source for this information are the many computer magazines (Byte, Dr. Dobb's Journal etc.) that were published in those times when MIPS calculations were actually used for benchmarking. The problem is that I don't have those magazines any more, that is why I have not fixed the article. --PauliKL (talk) 16:18, 13 April 2010 (UTC)

Well, pardon me if I wrongly interpreted "what do you mean by "instructions executed"? What instructions?" as a question on what I mean by instructions. It seems to me that you are confusing the metric with some benchmark. "MIPS" does not care what instructions are being executed. It's just a metric. It's like I was telling you that a kilometer equals 1000 meters and you insisted that no, you must define whether you are going to travel the kilometer on foot or by car. —ZeroOne (talk / @) 21:51, 13 April 2010 (UTC)

No, you are the one that is confusing things. Yes, MIPS is a metric, as I already told you. It is a metric of CPU speed. Not a metric of how many unspecified instructions are executed in whatever unspecified program. After all, such a "metric" would be pretty much useless (even if you find a way to count the instructions). Even the concept of "instruction" is vague. For example Pentium and Core 2 processors, even if called CISC processors, are actually RISC processors internally. The legacy CISC instructions are translated into RISC instructions before executing. Which instructions should you count, the CISC instructions in the code or the RISC instructions actually executed? And what about speculative execution?

In reality, MIPS definitely does care what instructions are being executed. This is because (in CISC processors) instruction execution times vary very much, for example from 1 to 50 clock cycles. That is exactly why MIPS calculation is done as weighted average. --PauliKL (talk) 16:10, 16 April 2010 (UTC)

Also my point holds even if RISC processors typically need 10 % more instructions than CISC processors. If an application requires 10 million instructions in CISC and 11 million in RISC and both execute the application in 1 second, then the CISC computer would have a MIPS value of 10 and the RISC computer a MIPS value of 11, even though they actually perform equally well.

—ZeroOne (talk / @) 10:19, 13 April 2010 (UTC)

No. If the application is a benchmark, and both processors get the same result (e.g. the same time), they both have the same result even when it is converted into MIPS value. For example, if it was Drystone test and both processors get the result 17570 dhrystones/sec, then both processors have Dhrystone MIPS rating of 10.0. The number of instructions they executed during the test has no effect on the results (and probably it is not even known). --PauliKL (talk) 16:18, 13 April 2010 (UTC)

Well, I, for one, was talking about the concept of MIPS, not about the concept of various benchmarks. Why are you switching between Dhrystone MIPS and VAX MIPS anyway? Also if a MIPS figure does not represent millions of instructions per second, like you said it doesn't in the case of Dhrystone, then it's pretty obvious to me that the acronym is being used in some other meaning than its original one. —ZeroOne (talk / @) 21:51, 13 April 2010 (UTC)

As I have explained, there are two possible ways to get MIPS rating:

1. Manually calculating a weighted average of instruction execution times for some specific reference instruction set (e.g. VAX instruction set, or older Gibson Mix or ADP Mix), or

2. Running a benchmark and then scaling the results into MIPS value (e.g. Dhrystone MIPS). In this case, MIPS is only used as a metric. Most of the values in the "Timeline of instructions per second" table (if not pulled out of hat) obviously come from benchmarks.

I have shown that whichever method is used, your arguments are wrong. MIPS is measure of CPU performance, it is not an instruction counter. MIPS does not care about how many instructions are executed in the target processor. RISC and CISC processors that have equal performance will get (approximately) equal MIPS rating regardles of how many instructions they happen to execute for some task. --PauliKL (talk) 16:10, 16 April 2010 (UTC)

I can't help but think that you are just dodging my questions or rephrasing what I (or you yourself) have been saying. How do you explain, for example, the definition of MIPS that Lilja gives in his book? Are you saying he is wrong? I gave you a claim with a source and you keep insisting on your own views, completely ignoring my points. —ZeroOne (talk / @) 10:16, 17 April 2010 (UTC)