I2C is a serial communication protocol used to connect low-speed peripherals to processors and microcontrollers. It was developed by Philips in the 1980s for use in televisions. I2C uses just two bidirectional open-drain lines: serial data line (SDA) and serial clock line (SCL). Devices can operate as master or slave devices and have a 7-bit address. Communication is initiated by the master which controls the clock signal. Data is transferred in one byte packets with acknowledgement from the receiver.
[cb22] Tales of 5G hacking by Karsten NohlCODE BLUE
An expert in mobile network security provided a summary of hacking 5G networks. Some key points include:
1) Standard IT security techniques uncovered issues when applied to upgraded legacy 4G networks, such as unpatched operating systems, weak configurations, and lack of encryption.
2) Future 5G networks introduce new security risks due to increased complexity from virtualization and automation layers, as well as a continuously evolving attack surface extending into cloud infrastructure.
3) Red team exercises show that hacking mobile networks has become a multi-step process, where initial access through one vulnerability can enable lateral movement and privilege escalation to compromise critical systems or customer data.
Define Width and Height of Core and Die (http://www.vlsisystemdesign.com/PD-F...VLSI SYSTEM Design
https://www.udemy.com/vlsi-academy
The very first step in chip design is floorplanning, in which the width and height of the chip, basically the area of the chip, is defined. A chip consists of two parts, 'core' and 'die'.
In this talk Jiří Pírko discusses the design and evolution of the VLAN implementation in Linux, the challenges and pitfalls as well as hardware acceleration and alternative implementations.
Jiří Pírko is a major contributor to kernel networking and the creator of libteam for link aggregation.
Semiconductor memory can be categorized based on attributes like read/write ability, storage permanence, and volatility. Common types include RAM, ROM, EEPROM, and flash memory. RAM is read/write and volatile, requiring power to maintain data. ROM is read-only and non-volatile, with data stored permanently. EEPROM and flash memory are read/write, non-volatile memories that retain data when powered off but with slower write speeds than RAM. Memory devices use architectures like rows and columns with decoders to access individual memory cells.
VLSI industry - Digital Design Engineers - draft versionMahmoud Abdellatif
This document discusses VLSI (Very Large Scale Integration) and becoming a digital design engineer. It begins by explaining what VLSI is, how integrated circuits are fabricated on silicon chips, and different design styles like full custom, ASICs, FPGAs, and SoCs. It then discusses why the VLSI industry is important and lists some major players. The document outlines different types of VLSI designers including those involved in EDA tool development, semiconductor research, design, and manufacturing. It provides an overview of the VLSI industry and career opportunities in Egypt. Finally, it offers advice on how to become a digital design engineer and start a career in the field through education and self-study of topics like digital design, V
PCI Express is a serial computer expansion bus standard designed to replace older standards like PCI and AGP. It uses point-to-point connections between two devices using serial communication over one or more lanes. PCIe protocol has three layers - the transaction layer which interacts with software, the data link layer which provides reliable packet exchange, and the physical layer which isolates the other layers from signaling technology.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
System on Chip (SoC) integrates processor, memory and other components onto a single chip. Advances in VLSI technology allow millions of transistors to be placed on a single die, enabling entire systems to be implemented as SoCs. This provides benefits like lower cost, power consumption and size compared to discrete components. However, designing highly complex SoCs presents challenges related to design time, verification and complexity. Reusing pre-designed and verified intellectual property (IP) cores is a solution that helps manage this complexity.
Static Timing Analysis is a process of checking timing violation of a design by checking all possible paths under worst conditions.Any deisgn with out meeting timing requirements is undesirable.STA plays vital role in chip designing .
The physical design flow begins with placement which involves assigning exact locations to modules like gates and standard cells to minimize area and interconnect cost while meeting timing constraints, with the goal of enabling easier routing; placement tools take as input the netlist, floorplan, libraries, and constraints to perform global and detailed placement as well as optimization. The quality of placement significantly impacts the ability to route the design successfully.
This document provides a summary of a book about PCI Express technology. It includes an introduction to the book, a table of contents listing the topics covered, biographies of the authors, and endorsements of the book. The summary is as follows:
The document introduces a book that provides a comprehensive guide to PCI Express generations 1.x, 2.x, and 3.0. It includes biographies of the authors and an endorsement quoting that the book is essential for understanding PCI Express. The table of contents indicates it will cover topics such as the origins and architecture of PCI Express, various technical specifications and features, and considerations for high-speed signaling.
This document discusses techniques for improving CPU access to data from IO devices, including Direct Cache Access (DCA), PCIe Transaction Layer Processing Hints (TPH), and Data Direct I/O (DDIO). DCA allows the CPU to access cache data from IO devices to avoid memory access, but requires driver intervention. PCIe TPH and DDIO aim to prefetch or retain IO write data in the cache without driver involvement. DDIO is specific to Intel platforms and accelerates local socket performance, while DCA does not differentiate sockets. The document provides details on how each technique functions and references further reading.
1. DPDK achieves high throughput packet processing on commodity hardware by reducing kernel overhead through techniques like polling, huge pages, and userspace drivers.
2. In Linux, packet processing involves expensive operations like system calls, interrupts, and data copying between kernel and userspace. DPDK avoids these by doing all packet processing in userspace.
3. DPDK uses techniques like isolating cores for packet I/O threads, lockless ring buffers, and NUMA awareness to further optimize performance. It can achieve throughput of over 14 million packets per second on 10GbE interfaces.
DPDK is a set of drivers and libraries that allow applications to bypass the Linux kernel and access network interface cards directly for very high performance packet processing. It is commonly used for software routers, switches, and other network applications. DPDK can achieve over 11 times higher packet forwarding rates than applications using the Linux kernel network stack alone. While it provides best-in-class performance, DPDK also has disadvantages like reduced security and isolation from standard Linux services.
A Hybrid Memory Data Cube Approach for High Dimension RelationsRodrigo Rocha Silva
Rodrigo Rocha Silva presented a paper on H-Frag, a hybrid memory approach for computing data cubes on high-dimensional relations. H-Frag extends the frag-cubing approach by storing portions of the computed data cube in external memory instead of relying solely on main memory. This allows for larger data cubes to be computed. H-Frag selects which fragments to store in main memory based on attribute value frequencies and dimension cardinalities. It generates inverted indexes of attribute values and stores low frequency values and their tid lists in external memory in order to compute cubes that exceed main memory capacity.
This presentation considers the changing nature of the scholarly record and applies the findings of NMC Horizons Report Library Edition 2014 to the Claremont Colleges Library's institutional repository.
La memoria RAM (Random Access Memory) es donde el computador guarda temporalmente los datos y programas que está utilizando actualmente. Está compuesta de chips o módulos de chips conectados a la tarjeta madre. Existen diferentes tipos de memoria RAM como SDRAM, DDR RAM, DDR2 RAM y So-DIMM que varían en tamaño, velocidad y número de pines.
1. The document provides resources for teaching algebra concepts such as variables, order of operations, and evaluating expressions.
2. It includes links to websites, videos, and images to demonstrate key ideas like PEMDAS and completing the square.
3. Students are expected to recognize multiple uses of variables, determine possible variable values, and evaluate algebraic expressions involving variables.
Old Fashioned Marketing in a New Fashioned WayUnique Venues
This document discusses effective old-fashioned marketing techniques for unique venues. It emphasizes knowing your purpose and audience, being creative and memorable, clearly calling to action, and using layered advertising across multiple mediums. Specific tips include bringing your venue's personality to life, leaving no questions, taking calculated risks to be uniquely memorable, and building recognition through a bold yet consistent brand. The focus is on climbing the awareness pyramid through steady efforts.
Baltimore, MD is first up in Unique Venues' series of meeting planning tip Infographics in the U.S. and Canada. Check out these tips and suggestions you might want to consider before planning an event in Baltimore.
Smart Mind Online Training is a leading IT training institution located in Hyderabad, India that provides online training courses for individuals and companies. They have experienced faculty who teach a wide range of technologies. Their goal is to train students for IT careers and provide 100% job assistance. They deliver customized training programs according to student and company needs.
Digital inequality refers to the gap between those who have access to the internet and digital skills and those who do not. The document discusses several factors that contribute to digital inequality, including gender, education, socioeconomic status, age, geography, and lack of access to technology or skills. The author focuses on addressing digital inequality among their students by providing solutions such as granting computers to check out, reconfiguring the computer lab schedule, offering broadband access, and implementing keyboarding practice and tech buddy programs to improve students' digital skills.
New Memory Solutions for Enterprise ComputingIntel IT Center
The document discusses memory solutions and trends in enterprise computing. It forecasts strong growth in the total available market for DRAM through 2016. It outlines opportunities for Micron to provide memory architectures like DDR4, small form factor DIMMs for microservers, and non-volatile DIMMs that combine DRAM and NAND flash.
In this presentation, Kevin Wagner from Diablo Technologies describes the company's new Memory Channel Flash Solution.
Diablo leveraged its extensive experience in advanced memory channel interfaces and protocols to deliver a superior system architecture that directly attaches persistent memory to the host processors of a server or storage array. This innovative approach utilizes the industry standard DIMM form factor and native CPU memory interface, allowing MCS to be a drop-in replacement for standard RDIMMs. The architecture delivers the highest, most economical scaling of any enterprise storage solution on the market today, with persistent latencies approaching that of DRAM and linear scaling of throughput with additional modules.
“Flash SSDs boost system performance, and flash over PCIe is even faster, but the best performance will come from flash on the memory channel," said Jim Handy, Director at Objective Analysis. "Diablo is on the right path by providing a way to plug flash right into the DDR memory buses on today's servers.”
View the presentation video: http://inside-bigdata.com/slidecast-diablo-memory-channel-flash-technology-is-big-data-for-less/
Supermicro Servers with Micron DDR5 & SSDs: Accelerating Real World WorkloadsRebekah Rodriguez
This document provides an overview of Supermicro's comprehensive server portfolio, including their rackmount, cloud, and mainstream server solutions. It highlights several multi-node server platforms like BigTwin, FatTwin, and GrandTwin. The document also mentions Supermicro will have many options for the upcoming 4th generation AMD EPYC 'Genoa' platform with support for up to 96 cores, 128 PCIe lanes, and DDR5 memory at up to 6TB capacity. In summary, the document outlines Supermicro's server product lines and upcoming support for the high-end 4th generation AMD EPYC processors.
Today Micron announced the production of 8GB DDR4 NVDIMM, the company’s first commercially available solution in the persistent memory category. Persistent memory delivers a unique balance of latency, bandwidth, capacity and cost, delivering ultra-fast DRAM-like access to critical data and allowing system designers to better manage overall costs. With persistent memory, system architects are no longer forced to sacrifice latency and bandwidth when accessing critical data that must be preserved.
Watch the video presentation: http://wp.me/p3RLHQ-eII
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
The document discusses in-memory computing and emerging technologies. It describes how in-memory applications are driving new storage class memory like 3D XPoint that has lower latency than NAND but higher capacity than DRAM. The document also discusses how in-memory solutions are using tiering of memory and storage like DRAM, 3D XPoint, NVM, and NAND to handle larger datasets. Emerging high speed fabrics and disaggregated storage are enabling more efficient scaling of memory and storage tiers independent of compute.
Analytics, Big Data and Nonvolatile Memory Architectures – Why you Should Car...StampedeCon
This session will begin with an overview of current non-volatile memory (NVM, aka persistent memory) architectures and its relationship between several levels of memory and storage hierarchy, both near- and far-processor. A discussion on its significant impact on computing analytic workloads now and in the near future will ensue, including use cases and the concept of very large persistent memory surfaces as applied to both analytic computation and storage for big data workflows. The presentation will end with ‘why you should care’ about such technologies which inevitably will completely change the way we think about solving data-intensive problems.
Fibre channel is on the rise, and the data center transformation is upon us! Join Brocade's Technical Development Manager, Mike Naylor as he explains how Brocade Gen5 Fabric can simplify your network infrastructure, reduce costs and maximize uptime.
Flash Roadblock: Latency! - How Storage Interconnects are Slowing Flash Storage Storage Switzerland
Flash storage is the “go to” option in the modern data center to overcome storage I/O bottlenecks. The problem has been how to get full performance for the flash investment. The zero latent nature of flash exposes bottlenecks throughout the I/O chain.
In this webinar you will learn:
• How latency is introduced by each flash interconnect
• What the performance ramifications are of this latency
• How to reach the full performance potential of flash based storage by leveraging the memory bus
• How memory bus based flash changes the game for how flash can be utilized in the data center
Dror Goldenberg from Mellanox presented this deck at the HPC Advisory Council Switzerland Conference.
“High performance computing has begun scaling beyond Petaflop performance towards the Exaflop mark. One of the major concerns throughout the development toward such performance capability is scalability – at the component level, system level, middleware and the application level. A Co-Design approach between the development of the software libraries and the underlying hardware can help to overcome those scalability issues and to enable a more efficient design approach towards the Exascale goal.”
Watch the video presentation: http://wp.me/p3RLHQ-f7s
See more talks in the Swiss Conference Video Gallery:
http://insidehpc.com/2016-swiss-hpc-conference/
Sign up for our insideHPC Newsletter:
http://insidehpc.com/newsletter
How Persistent Memory Will Bring an Entirely New Structure to Large Data Comp...inside-BigData.com
In this deck from the Persistent Memory Summit 2017, Steve Pawlowski from Micron presents:
The Revolution of Memory and Storage Side Processing - How Persistent Memory Will Bring an Entirely New Structure to Large Data Computing.
"As data proliferation continues to explode, computing architectures are struggling to get the right data to the processor efficiently, both in terms of time and power. But what if the best solution to the problem is not faster data movement, but new architectures that can essentially move the processing instructions into the data? Persistent memory arrays present just such an opportunity. Like any significant change, however, there are challenges and obstacles that must be overcome. Industry veteran Steve Pawlowski will outline a vision for the future of computing and why persistent memory systems have the potential to be more revolutionary than perhaps anyone imagines."
Watch the video presentation: http://wp.me/p3RLHQ-gff
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Mellanox is a leading provider of high-performance interconnect solutions including InfiniBand and Ethernet technologies. It has over 1,200 employees worldwide and reported record revenue in 2012 of $500.8 million, up 93% year-over-year. Mellanox's interconnect solutions reduce application wait times for data and increase ROI on data center infrastructure.
HAMR, HDMR, DuraWrite, SHIELD, RAISE sind Technologien, mit denen Seagate der stetig wachsenden Datenmenge in Unternehmen entgegen tritt. Im Webinar erfahren Sie direkt vom Hersteller, was sich dahinter verbirgt.
In this deck, Gilad Shainer from Mellanox provides an overview of new products for the SC15 conference.
Learn more: http://mellanox.com
Watch the video presentation: http://wp.me/p3RLHQ-eJu
Sign up for our insideHPC Newsletter
Silicon Motion is a global fabless semiconductor company established in 1995 with over 1200 employees that specializes in NAND flash controllers, solutions, and graphic display SoCs. The document provides an overview of Silicon Motion including their product categories, market share in client SSD controllers and embedded storage solutions, competitive advantages including reliability and support for automotive and industrial applications, and technology advantages such as error correction and extending NAND lifespan.
The document discusses how Mellanox storage solutions can maximize data center return on investment through faster database performance, increased virtual machine density per server, and lower total cost of ownership. Mellanox's high-speed interconnect technologies like InfiniBand and RDMA can provide over 10x higher storage performance compared to traditional Ethernet and Fibre Channel solutions.
Watch the full webinar here: http://bit.ly/1TUuUCK
When considering flash storage, there are many misconceptions and outright myths. Especially when equating consumer-grade flash (USB sticks) to enterprise-grade SSDs. In this webinar SanDisk Chief Architect, Adam Roberts, will discuss 5 myths of flash storage and highlight what you need to look out for when choosing a storage device to accelerate your data center storage. This webinar will cover:
1.Data Protection
2.Power Fail Protection
3.Temperature Throttling/Overheating
4.QoS for Performance
5.SSD Endurance
Stay tuned for future webinars which will look at the benefits of flash beyond performance…busting a few more myths on flash.
IBM FlashSystem and other SSD's are being adopted for OLTP and Analytics applications. Fast 16Gb Flash storage requires a reliable, high performance network to ensure applications can utilize it effectively. Learn how to plan for a highspeed reliable network to handle the increased demands while delivering reliable application response times. Understand the reliability, performance, and simplified management features of Gen5 FC and Fabric Vision. Be prepared for the next jump in SAN's.
The document summarizes emerging computing trends in data centers, including:
1) The shift to multi-core CPU designs after Dennard scaling broke down, driven by the need for energy efficient designs for cloud computing.
2) The rise of heterogeneous computing using application-specific accelerators like GPUs and FPGAs to improve efficiency for targeted workloads like machine learning.
3) How technologies developed for mobile and edge computing like ARM cores can improve data center server efficiency through typical-use optimization rather than just peak performance.
Similar to Hybrid Memory Cube: Developing Scalable and Resilient Memory Systems (20)
Implementations of Fused Deposition Modeling in real worldEmerging Tech
The presentation showcases the diverse real-world applications of Fused Deposition Modeling (FDM) across multiple industries:
1. **Manufacturing**: FDM is utilized in manufacturing for rapid prototyping, creating custom tools and fixtures, and producing functional end-use parts. Companies leverage its cost-effectiveness and flexibility to streamline production processes.
2. **Medical**: In the medical field, FDM is used to create patient-specific anatomical models, surgical guides, and prosthetics. Its ability to produce precise and biocompatible parts supports advancements in personalized healthcare solutions.
3. **Education**: FDM plays a crucial role in education by enabling students to learn about design and engineering through hands-on 3D printing projects. It promotes innovation and practical skill development in STEM disciplines.
4. **Science**: Researchers use FDM to prototype equipment for scientific experiments, build custom laboratory tools, and create models for visualization and testing purposes. It facilitates rapid iteration and customization in scientific endeavors.
5. **Automotive**: Automotive manufacturers employ FDM for prototyping vehicle components, tooling for assembly lines, and customized parts. It speeds up the design validation process and enhances efficiency in automotive engineering.
6. **Consumer Electronics**: FDM is utilized in consumer electronics for designing and prototyping product enclosures, casings, and internal components. It enables rapid iteration and customization to meet evolving consumer demands.
7. **Robotics**: Robotics engineers leverage FDM to prototype robot parts, create lightweight and durable components, and customize robot designs for specific applications. It supports innovation and optimization in robotic systems.
8. **Aerospace**: In aerospace, FDM is used to manufacture lightweight parts, complex geometries, and prototypes of aircraft components. It contributes to cost reduction, faster production cycles, and weight savings in aerospace engineering.
9. **Architecture**: Architects utilize FDM for creating detailed architectural models, prototypes of building components, and intricate designs. It aids in visualizing concepts, testing structural integrity, and communicating design ideas effectively.
Each industry example demonstrates how FDM enhances innovation, accelerates product development, and addresses specific challenges through advanced manufacturing capabilities.
In this follow-up session on knowledge and prompt engineering, we will explore structured prompting, chain of thought prompting, iterative prompting, prompt optimization, emotional language prompts, and the inclusion of user signals and industry-specific data to enhance LLM performance.
Join EIS Founder & CEO Seth Earley and special guest Nick Usborne, Copywriter, Trainer, and Speaker, as they delve into these methodologies to improve AI-driven knowledge processes for employees and customers alike.
Video traffic on the Internet is constantly growing; networked multimedia applications consume a predominant share of the available Internet bandwidth. A major technical breakthrough and enabler in multimedia systems research and of industrial networked multimedia services certainly was the HTTP Adaptive Streaming (HAS) technique. This resulted in the standardization of MPEG Dynamic Adaptive Streaming over HTTP (MPEG-DASH) which, together with HTTP Live Streaming (HLS), is widely used for multimedia delivery in today’s networks. Existing challenges in multimedia systems research deal with the trade-off between (i) the ever-increasing content complexity, (ii) various requirements with respect to time (most importantly, latency), and (iii) quality of experience (QoE). Optimizing towards one aspect usually negatively impacts at least one of the other two aspects if not both. This situation sets the stage for our research work in the ATHENA Christian Doppler (CD) Laboratory (Adaptive Streaming over HTTP and Emerging Networked Multimedia Services; https://athena.itec.aau.at/), jointly funded by public sources and industry. In this talk, we will present selected novel approaches and research results of the first year of the ATHENA CD Lab’s operation. We will highlight HAS-related research on (i) multimedia content provisioning (machine learning for video encoding); (ii) multimedia content delivery (support of edge processing and virtualized network functions for video networking); (iii) multimedia content consumption and end-to-end aspects (player-triggered segment retransmissions to improve video playout quality); and (iv) novel QoE investigations (adaptive point cloud streaming). We will also put the work into the context of international multimedia systems research.
AC Atlassian Coimbatore Session Slides( 22/06/2024)apoorva2579
This is the combined Sessions of ACE Atlassian Coimbatore event happened on 22nd June 2024
The session order is as follows:
1.AI and future of help desk by Rajesh Shanmugam
2. Harnessing the power of GenAI for your business by Siddharth
3. Fallacies of GenAI by Raju Kandaswamy
Fluttercon 2024: Showing that you care about security - OpenSSF Scorecards fo...Chris Swan
Have you noticed the OpenSSF Scorecard badges on the official Dart and Flutter repos? It's Google's way of showing that they care about security. Practices such as pinning dependencies, branch protection, required reviews, continuous integration tests etc. are measured to provide a score and accompanying badge.
You can do the same for your projects, and this presentation will show you how, with an emphasis on the unique challenges that come up when working with Dart and Flutter.
The session will provide a walkthrough of the steps involved in securing a first repository, and then what it takes to repeat that process across an organization with multiple repos. It will also look at the ongoing maintenance involved once scorecards have been implemented, and how aspects of that maintenance can be better automated to minimize toil.
AI_dev Europe 2024 - From OpenAI to Opensource AIRaphaël Semeteys
Navigating Between Commercial Ownership and Collaborative Openness
This presentation explores the evolution of generative AI, highlighting the trajectories of various models such as GPT-4, and examining the dynamics between commercial interests and the ethics of open collaboration. We offer an in-depth analysis of the levels of openness of different language models, assessing various components and aspects, and exploring how the (de)centralization of computing power and technology could shape the future of AI research and development. Additionally, we explore concrete examples like LLaMA and its descendants, as well as other open and collaborative projects, which illustrate the diversity and creativity in the field, while navigating the complex waters of intellectual property and licensing.
The DealBook is our annual overview of the Ukrainian tech investment industry. This edition comprehensively covers the full year 2023 and the first deals of 2024.
Paradigm Shifts in User Modeling: A Journey from Historical Foundations to Em...Erasmo Purificato
Slide of the tutorial entitled "Paradigm Shifts in User Modeling: A Journey from Historical Foundations to Emerging Trends" held at UMAP'24: 32nd ACM Conference on User Modeling, Adaptation and Personalization (July 1, 2024 | Cagliari, Italy)
MYIR Product Brochure - A Global Provider of Embedded SOMs & SolutionsLinda Zhang
This brochure gives introduction of MYIR Electronics company and MYIR's products and services.
MYIR Electronics Limited (MYIR for short), established in 2011, is a global provider of embedded System-On-Modules (SOMs) and
comprehensive solutions based on various architectures such as ARM, FPGA, RISC-V, and AI. We cater to customers' needs for large-scale production, offering customized design, industry-specific application solutions, and one-stop OEM services.
MYIR, recognized as a national high-tech enterprise, is also listed among the "Specialized
and Special new" Enterprises in Shenzhen, China. Our core belief is that "Our success stems from our customers' success" and embraces the philosophy
of "Make Your Idea Real, then My Idea Realizing!"
this resume for sadika shaikh bca studentSadikaShaikh7
I am a dedicated BCA student with a strong foundation in web technologies, including PHP and MySQL. I have hands-on experience in Java and Python, and a solid understanding of data structures. My technical skills are complemented by my ability to learn quickly and adapt to new challenges in the ever-evolving field of computer science.
Are you interested in learning about creating an attractive website? Here it is! Take part in the challenge that will broaden your knowledge about creating cool websites! Don't miss this opportunity, only in "Redesign Challenge"!
UiPath Community Day Kraków: Devs4Devs ConferenceUiPathCommunity
We are honored to launch and host this event for our UiPath Polish Community, with the help of our partners - Proservartner!
We certainly hope we have managed to spike your interest in the subjects to be presented and the incredible networking opportunities at hand, too!
Check out our proposed agenda below 👇👇
08:30 ☕ Welcome coffee (30')
09:00 Opening note/ Intro to UiPath Community (10')
Cristina Vidu, Global Manager, Marketing Community @UiPath
Dawid Kot, Digital Transformation Lead @Proservartner
09:10 Cloud migration - Proservartner & DOVISTA case study (30')
Marcin Drozdowski, Automation CoE Manager @DOVISTA
Pawel Kamiński, RPA developer @DOVISTA
Mikolaj Zielinski, UiPath MVP, Senior Solutions Engineer @Proservartner
09:40 From bottlenecks to breakthroughs: Citizen Development in action (25')
Pawel Poplawski, Director, Improvement and Automation @McCormick & Company
Michał Cieślak, Senior Manager, Automation Programs @McCormick & Company
10:05 Next-level bots: API integration in UiPath Studio (30')
Mikolaj Zielinski, UiPath MVP, Senior Solutions Engineer @Proservartner
10:35 ☕ Coffee Break (15')
10:50 Document Understanding with my RPA Companion (45')
Ewa Gruszka, Enterprise Sales Specialist, AI & ML @UiPath
11:35 Power up your Robots: GenAI and GPT in REFramework (45')
Krzysztof Karaszewski, Global RPA Product Manager
12:20 🍕 Lunch Break (1hr)
13:20 From Concept to Quality: UiPath Test Suite for AI-powered Knowledge Bots (30')
Kamil Miśko, UiPath MVP, Senior RPA Developer @Zurich Insurance
13:50 Communications Mining - focus on AI capabilities (30')
Thomasz Wierzbicki, Business Analyst @Office Samurai
14:20 Polish MVP panel: Insights on MVP award achievements and career profiling
Performance Budgets for the Real World by Tammy EvertsScyllaDB
Performance budgets have been around for more than ten years. Over those years, we’ve learned a lot about what works, what doesn’t, and what we need to improve. In this session, Tammy revisits old assumptions about performance budgets and offers some new best practices. Topics include:
• Understanding performance budgets vs. performance goals
• Aligning budgets with user experience
• Pros and cons of Core Web Vitals
• How to stay on top of your budgets to fight regressions
What Not to Document and Why_ (North Bay Python 2024)Margaret Fero
We’re hopefully all on board with writing documentation for our projects. However, especially with the rise of supply-chain attacks, there are some aspects of our projects that we really shouldn’t document, and should instead remediate as vulnerabilities. If we do document these aspects of a project, it may help someone compromise the project itself or our users. In this talk, you will learn why some aspects of documentation may help attackers more than users, how to recognize those aspects in your own projects, and what to do when you encounter such an issue.
These are slides as presented at North Bay Python 2024, with one minor modification to add the URL of a tweet screenshotted in the presentation.
Coordinate Systems in FME 101 - Webinar SlidesSafe Software
If you’ve ever had to analyze a map or GPS data, chances are you’ve encountered and even worked with coordinate systems. As historical data continually updates through GPS, understanding coordinate systems is increasingly crucial. However, not everyone knows why they exist or how to effectively use them for data-driven insights.
During this webinar, you’ll learn exactly what coordinate systems are and how you can use FME to maintain and transform your data’s coordinate systems in an easy-to-digest way, accurately representing the geographical space that it exists within. During this webinar, you will have the chance to:
- Enhance Your Understanding: Gain a clear overview of what coordinate systems are and their value
- Learn Practical Applications: Why we need datams and projections, plus units between coordinate systems
- Maximize with FME: Understand how FME handles coordinate systems, including a brief summary of the 3 main reprojectors
- Custom Coordinate Systems: Learn how to work with FME and coordinate systems beyond what is natively supported
- Look Ahead: Gain insights into where FME is headed with coordinate systems in the future
Don’t miss the opportunity to improve the value you receive from your coordinate system data, ultimately allowing you to streamline your data analysis and maximize your time. See you there!
How Netflix Builds High Performance Applications at Global ScaleScyllaDB
We all want to build applications that are blazingly fast. We also want to scale them to users all over the world. Can the two happen together? Can users in the slowest of environments also get a fast experience? Learn how we do this at Netflix: how we understand every user's needs and preferences and build high performance applications that work for every user, every time.
Are you interested in dipping your toes in the cloud native observability waters, but as an engineer you are not sure where to get started with tracing problems through your microservices and application landscapes on Kubernetes? Then this is the session for you, where we take you on your first steps in an active open-source project that offers a buffet of languages, challenges, and opportunities for getting started with telemetry data.
The project is called openTelemetry, but before diving into the specifics, we’ll start with de-mystifying key concepts and terms such as observability, telemetry, instrumentation, cardinality, percentile to lay a foundation. After understanding the nuts and bolts of observability and distributed traces, we’ll explore the openTelemetry community; its Special Interest Groups (SIGs), repositories, and how to become not only an end-user, but possibly a contributor.We will wrap up with an overview of the components in this project, such as the Collector, the OpenTelemetry protocol (OTLP), its APIs, and its SDKs.
Attendees will leave with an understanding of key observability concepts, become grounded in distributed tracing terminology, be aware of the components of openTelemetry, and know how to take their first steps to an open-source contribution!
Key Takeaways: Open source, vendor neutral instrumentation is an exciting new reality as the industry standardizes on openTelemetry for observability. OpenTelemetry is on a mission to enable effective observability by making high-quality, portable telemetry ubiquitous. The world of observability and monitoring today has a steep learning curve and in order to achieve ubiquity, the project would benefit from growing our contributor community.